The present invention relates, in general, to electrical circuits, and more particularly, to a novel voltage translator circuit.
In the past, voltage translator circuits have been utilized to translate the voltage level of emitter coupled logic (ECL) signals to voltage levels that are compatible with transistor-transistor logic (TTL), complementary metal oxide semiconductor (CMOS) logic, or other compatible signals. Prior translators typically employ an input stage that receives a differential ECL signal, and uses the input signal to control a pair of transistors connected in series between two power supply terminals. Such series connected transistors are commonly referred to as a totem-pole output stage. As the differential input signal changes state, the upper and lower transistors of the output stage are often simultaneously enabled thereby permitting large currents to flow through both output transistors. These large currents, commonly referred to as "through" current, increase power dissipation, induce noise into the power supply and can disturb the operation of adjacent circuits.
Accordingly, it is desirable to have a voltage translator circuit that does not simultaneously enable both output transistors, that substantially eliminates "through" current, and that does not induce noise into the power supply.